1. Field of the Invention
The present invention relates generally to flexible modular integrated circuit embodiments, and more specifically to a structured framework for constructing and interfacing variable mixtures of computer processors, memories, peripherals, and other functional modules on a single semiconductor integrated circuit.
2. Description of the Prior Art
As systems-on-chip (SoC) become more complex, it will be increasingly difficult for a single company to provide its customers with all of the intellectual-property (IP) cores and library macrocells they require. Companies have to evaluate whether human resources, capital and time are expendable on extraneous developments. A growing trend is to outsource the areas that fall outside of their core competencies.
Time-to-market is the dominant factor directing this make vs. buy decision. SoCs are reaching higher levels of integration, but their complexity is inversely proportional to the allowable time-to-market. xe2x80x9cBuyingxe2x80x9d semiconductor IP will become essential for surviving in an environment that demands increased profits and decreased time-to-market. For companies to meet the technology challenges of integrating externally developed semiconductor IP into a single chip, within the given time window, they will have to partner with others, including, in some cases, their competitors.
Outsourcing and partnership will be the essential elements of a successful semiconductor business in the next century because those capabilities will help companies deliver what customers want. Companies using SoC technologies have recognized the need to license or buy IP from other companies. But just purchasing the IP is not enough. Integrating IP in a system-on-chip is complicated, especially when components from multiple sources are involved. IP integrators and providers need to actively work together to make sure that all of the pieces of the SoC fit seamlessly. One way to leverage the strength of a partnership is by offering an open architecture.
Successful semiconductor companies must be able to deliver to the customer an on-chip architecture, in which components can be dropped in and interconnected with little difficulty. Open means that it is supported by third-party companies, thereby producing a collaborative effort to reduce the design-integration struggles found in SoC development, including hardware and software codesign and coverification. That also results in reducing time-to-market. Customers will have choices in how they build their SoC devices, which IP components to integrate, and what software and operating system to implement. Outsourcing and partnership are keys to successfully offering customers what they want. Taking this a step further, providing and/or supporting an open architecture gives customers the flexibility they need.
The electronics industry has been driven by the need to increase performance, reduce costs and enhance features. Many of these needs have been met through the use of newer, faster and cheaper technologies. Newer technologies continue to allow for more functions and features to be placed on a single piece of silicon. Functions that previously were placed on separate chips can now be integrated in a system-on-chip with new functions added.
In any processor-driven embodiment, a number of peripheral devices are needed. These include timers, DMA engines, interrupt controllers and memory controllers. In many cost-sensitive applications, a shared memory structure is preferably used to reduce memory component costs. An architecture is needed which addresses the memory needs of all devices without severely degrading the performance of any single device.
The PCIbus, ISA, VMEbus, and most other buses were designed as, system level buses to connect discrete devices on a printed circuit board (PCB) substrate. At the board level, a key issue is minimizing the number of bus signals because pin and signal count translate directly into package and PCB costs. A large number of device pins increases package footprint and reduces component density on the board. System level buses must support add-in cards and PCB backplanes where connector size and cost are also directly related to signal count. This is why traditional system level buses use shared tri-state signaling and, in the case of PCIbus, multiplexed address and data on the same signals. Timing problems can be investigated in the lab using prototype PCBs that can then be modified and re-spun in a few days.
In the on-chip world, signal routing consumes silicon area but does not affect the size or cost of packages, PCBs and connectors. The limited capabilities of today""s logic synthesis tools directly impact embodiment time and performance and must be taken into account. Getting the lowest possible routing overhead is of little value if the system design time balloons way out of proportion and the market window is missed. Synthesis tools find it difficult to deal with shared tri-state signals with several drivers and receivers connected to the same trace. Static timing analysis is preferably awkward, and often the only way to verify timing is to use a circuit level simulator such as Spice. All of this takes time and effort without adding real value in terms of device functionality or features. Bus loading also limits theoretical performance and the verification problems associated with bus loading can lead to a conservative embodiment whose performance falls short of the inherent technology capabilities.
The on-chip world has a significantly different set of embodiment constraints and tradeoffs compared with the board-level environment. A bus designed for use on PCBs will not provide the most efficient on-chip solution. When we started the embodiment of our GreenLite hard disk controller core we quickly realized that we needed to create a completely new bus architecture optimized for systems-on-silicon. The key issues were performance, embodiment time reduction, ease of use, power consumption and silicon efficiency. The following sections describe embodiments of the present invention and show how we satisfied these requirements.
It is therefore an object of the present invention to provide a system-on-chip interconnection structure and method for efficient integration of a variety of functional circuits.
It is a further object of the present invention to provide an on-chip interconnect architecture that standardizes how systems-on-chip are fabricated on silicon semiconductor integrated circuit chips.
Briefly, a system-on-chip interconnection structure and method embodiment of the present invention uses unidirectional buses only, central shared memory controllers, separate interconnects for high-speed and low-speed peripherals, zero wait-state register accesses, application-specific memory map and peripherals, application-specific test methodology, allowances for cache controllers, and good fits with standard ASIC flow and tools.
An advantage of the present invention is that a system is provided that enables electronics applications to be developed quickly and to be portable between silicon foundries.
Another advantage of the present invention is that a system is provided that can run at higher clock speeds.